The present invention relates to a semiconductor memory device, and more particularly to a non-volatile semiconductor memory device provided with a differential sense amplifier.
In non-volatile semiconductor memory devices provided with a differential sense amplifier, for instance such as ultraviolet light erasable programmable read-only-memories (EPROM), a potential read according to a memory data stored in a memory cell selected by an address is compared with a reference potential read from a reference (dummy) cell by the sense amplifier, to determine whether the stored data level is "1" or "0".
In the EPROM as described above, the total capacity of a plurality of dummy capacity cells DC each of whose drain terminals is connected to a reference (dummy) bit line DBL is so determined that the capacity produced at each bit line BL is roughly equal to that produced at the dummy bit line DBL.
Recently, on the other hand, redundancy techniques whereby a memory device including some defective memory cells is usable as a non-defective memory device have been widely adopted with remarkably increasing memory capacity. In the EPROM, therefore, it has become important more and more to alleviate not only the row defectiveness but also the column defectiveness, in particular. In this case, in addition to memory cells arranged in m (rows) x n (columns) matrix form, a plurality of redundancy cell columns are provided by arranging the same memory cells in m-column form. In case one of the memory cells MC arranged in m (rows) x n (columns) matrix form is defective and further a column address for selecting a cell column including a defective memory cell is inputted, one of the redundancy cell columns is selected, instead of the cell column including the defective cell memory, for relief of the defective memory cell.
The EPROM is usually provided with a current drive capability in the output buffer circuit, in order to generate an output compatible with that of a transistor-transistor logic circuit TTL. Therefore, when data are outputted, potential fluctuations (noise) occur on an inner voltage supply line within a chip. To suppress the above noise, a method has so far been proposed whereby the voltage supply line for the output buffer circuits is separated from that for the other inner circuits. In this method of separating the two voltage supply lines, however, it is impossible to perfectly suppress the occurrence of the above-mentioned noise. Once noise is generated on the voltage supply line, since each potential at each node of the inner circuit to which voltage is supplied via the voltage supply line fluctuates, potentials of the bit lines BL, the reference bit lines DBL, the sense line SL, and the reference potential line RL all change according to supply voltage fluctuations.
In the prior-art EPROM, a plurality of dummy capacity cells DC are connected to the reference bit line DBL so that the capacity produced at each bit line for selecting a memory cell MC arranged in m (rows) x n (columns) matrix form is equal to that produced at the reference bit line DBL. Therefore, in case the supply voltage Vcc fluctuates, since the potential V.sub.R on the reference potential line RL connected to the reference cells fluctuates in synchronism with that V.sub.S at the sense line SL generated whenever data are read out of the memory cells MC, there exists no problem in that the data read out of the memory cells MC are erroneously determined to be "1" or "0".
In general, however, since the capacity produced on the redundancy bit line to which drains of cells of the redundancy cell column is not determined equal to that produced on the reference bit line DBL, when a redundancy cell column is selected when the supply voltage is fluctuating, the potential V.sub.R on the reference potential line RL does not necessarily fluctuate in synchronism with that V.sub.S on the sense line SL, thus resulting in a problem in that the read data potential level is erroneously determined to be "1" or "0".